Semiconductor devices find a wide range of applications in the electronics industry. For example, transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A Fin field-effect transistor (FinFET) is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FinFET is a three dimensional transistor formed with a thin fin that extends upwardly from a semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FinFET the transistor channel is formed along the vertical sidewalls of the fin or on both vertical sidewalls and the top horizontal plane of the fin, so a wide channel, and hence high performance, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
FinFETs provide a promising candidate for small line width technology (e.g., approximately 22 nm and below) because of their excellent short channel effect control and scalability. For future technology nodes, high mobility III-V channel materials may be desired, with the fins including the III-V channel materials in the channel region of the fins. The III-V channel material may be epitaxially-grown on a semiconductor substrate, such as a silicon substrate. However, due to differences in the crystal lattices between the III-V materials and silicon, unwanted defects are generally prevalent at a portion of the fin that is proximal to the semiconductor substrate.
Further, isolating individual devices in a circuit becomes increasingly complex as device density increases. Conventional device isolation is accomplished through use of well implants to form NMOS and PMOS regions and deep-etched shallow trench isolation (STI) regions to separate the NMOS and PMOS regions. However, it is desirable to electrically decouple the fins from the semiconductor substrate to further enhance device to device isolation.
Accordingly, it is desirable to provide semiconductor devices and methods of forming the semiconductor devices having fins with a portion thereof including III-V semiconductor material while minimizing defects in the fin due to differences in crystal lattices between the III-V materials and the material of a semiconductor substrate. It is also desirable to provide such semiconductor devices with the portion of the fin including the III-V semiconductor material electrically decoupled from the semiconductor substrate to minimize unwanted leakage and improve isolation. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.